DRAM-based Coherent Caches and how to take advantage of the coherence protocol to reduce the refresh power

The introduction of FinFET technology has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper is the first one to propose the implementation of coherent caches with DRAM cells. Furthermore, we propose to use the coherence state to tune the refresh overhead. According to our analysis, an average of 16% and up to 24% of refresh energy can be saved with a performance loss below 6%. Also, comparing to the caches implemented in SRAMs total energy savings are on average 45% and up to 61%.